Capacitor and method for fabricating the same

ABSTRACT

A capacitor structure and a method of fabricating the capacitor structure wherein. The lower electrode and the upper electrode are constructed to be separated from each other by a predetermined interval and to be engaged with each other using a series of alternating ridges so that an effective surface area can increase within a limited area.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Korean Patent Application No.10-2004-0117006, filed on Dec. 30, 2004, which is hereby incorporated byreference as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to capacitors, and more particularly, to acapacitor and a method for fabricating the same, which increases aneffective surface area through a simplified process.

2. Discussion of the Related Art

A unit cell of a semiconductor device is generally constructed with onetransistor and one capacitor for storing an electrical charge as a unitof memory. As device integration increases, the area of the unit celldecreases. However, while the capacitor's layout area should beminimized, a sufficient capacitance must be maintained. These goals maybe achieved by, for example, using a thinner dielectric or higher-kdielectrics. However, a dielectric layer of an ultra thin film tends todeteriorate reliability while higher-k materials usually require specialprocessing. Therefore, a preferred approach is to increase thecapacitor's effective surface area, i.e. the total area of opposinglower and upper electrodes abutting an insulating layer.

A typical capacitor uses a polysilicon-insulator-polysilicon structure,and a method of reaching such a structure is illustrated in FIG. 1.

Referring to FIG. 1, a lower polysilicon 11, a dielectric layer 12, andan upper polysilicon 13 are sequentially deposited on a semiconductorsubstrate 10 where interconnection lines, and a planarization layer maybe formed. The lower polysilicon layer 11 serves as the lower electrodeof a capacitor, and the upper electrode may be formed by patterning anupper polysilicon 13 by a typical photolithography process.

After the upper polysilicon 13 is patterned to form the upper electrodeof the capacitor on the substrate 10, the dielectric layer 12 and thelower polysilicon 11 are patterned to form the dielectric member and thelower electrode of the capacitor. Similar to the pattering of the upperpolysilicon 13, the patterning of the dielectric layer 12 and the lowerpolysilicon 11 are performed by using a typical photolithographyprocess, i.e. a process that involves forming a photosensitive film onthe substrate 10 where the upper polysilicon 13 is patterned, exposingand developing using a mask to form a pattern of the photosensitivefilm, etching the dielectric layer 12 and the lower polysilicon 11exposed by the pattern of the photosensitive film, and removing aremaining pattern of the photosensitive film.

The insulating layer 14 and the planarization layer 15 are formed on thesubstrate 10 where the capacitor constructed with the lower electrode,the dielectric member, and the upper electrode is formed. After that,the planarization layer 15 and the insulating layer 14 are etched toform contact holes for exposing the upper polysilicon 13 and the lowerpolysilicon 11. Similar to the patterning of the upper polysilicon 13,the etching of the insulating layer 14 and the planarization layer 15 isperformed by using a typical photolithography process, i.e. by forming aphotosensitive film, exposing and developing using a mask to form apattern of the photosensitive film, etching the planarization layer 15and the underlying insulating layer 14 exposed by the pattern of thephotosensitive film, and removing a remaining pattern of thephotosensitive film.

A conductive material filling the contact hole is then formed andpatterned on the substrate 10 where the contact hole is formed. Next, aground node 16 electrically connected to the lower polysilicon 11 and apower supply node 17 electrically connected to the upper polysilicon 13are formed. The patterning of the conductive material may likewise beperformed by using a typical photolithography process.

The method for fabricating a capacitor as described above, requires atleast four photolithography steps and seven deposition steps whichunduly complicate the process and increase production costs. Inaddition, the lower electrode and the upper electrode are stacked in aplanar structure, making for a large layout of the unit cell.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a capacitor and amethod of fabricating the same that substantially obviates one or moreproblems due to limitations and disadvantages of the related art.

One advantage of the present invention is that it can provide acapacitor and a method of fabricating the same capable of forming acapacitor by using a minimized number of processes.

Another advantage of the present invention is that it can provide acapacitor and a method of fabricating the same capable of increasing aneffective surface area of a capacitor.

Another advantage of the present invention is that it can provide acapacitor and a method of fabricating the same capable of implementing acapacitor having a high capacitance in a limited area of a unit cell.

Additional advantages and features of the invention will be set forth inpart in the description which follows, and in part will become apparentfrom the description or by practice of the invention.

To achieve these and other advantages in accordance with an embodimentof the present invention, as embodied and broadly described herein, acapacitor structure comprises a lower electrode, constructed of a firstpolysilicon layer patterned in a series of ridges by implanting firstconductivity type impurity ions and forming a first silicide layerstacked on an upper portion of the first polysilicon layer, an upperelectrode, constructed of a second polysilicon layer patterned in aseries of ridges by implanting second conductivity type impurity ionsand a second silicide layer stacked on an upper portion of the secondpolysilicon layer, the upper electrode being separated from the lowerelectrode by a predetermined interval and being engaged with the lowerelectrode, and a dielectric layer separating the lower and upperelectrodes.

According to another aspect of the present invention, a method offabricating a capacitor structure, comprises patterning polysilicon on asubstrate, performing an ion implantation process in which ions areimplanted in the patterned polysilicon, the implanted ions includingfirst conductivity type impurity ions and second conductivity typeimpurity ions forming a first region in which the first conductivitytype impurity ions are implanted, a second region in which the secondconductivity type impurity ions are implanted, and a third region inwhich the first conductivity type impurity ions and the secondconductivity type impurity ions are simultaneously implanted wherein thethird region is a boundary region between the first region and thesecond region, forming a silicide layer on the first region and thesecond region, etching the third region to expose the substrate, andforming a dielectric layer in the etched third region.

It is to be understood that both the foregoing general description andthe following detailed description of the present invention areexemplary and explanatory and are intended to provide furtherexplanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this specification, illustrate embodiment(s) of the inventionand together with the description serve to explain the principles of theinvention.

In the drawings:

FIG. 1 is a schematic cross-sectional view of a typicalpolysilicon-insulator-polysilicon capacitor; and

FIGS. 2A-2F are views of a polysilicon-insulator-polysilicon capacitor,respectively illustrating sequential steps of a method for fabricating acapacitor according to exemplary embodiments of the present invention,in which each drawing includes a planar view and a cross-sectional viewalong line I-I′ or line II-II′ of the planar view.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to exemplary embodiments of thepresent invention, examples of which are illustrated in the accompanyingdrawings. Wherever possible, like reference designations will be usedthroughout the drawings to refer to the same or similar parts.

As shown in FIG. 2A, a polysilicon 21 is deposited on a substrate 20 andthen patterned. The process for depositing and patterning thepolysilicon 21 is simultaneously performed with a depositing andpatterning process for forming a gate electrode of a semiconductordevice, i.e. a metal-oxide-silicon (MOS) transistor, formed on thesubstrate 20.

As shown in FIG. 2B, N-type impurity ions and P-type impurity ions areimplanted into the polysilicon 21 to form a first region N+ in which theN-type impurity ions are implanted and a second region P+ in which theP-type impurity ions are implanted, and at the same time, to form athird region (N+, P+) in which the N-type impurity ions and the P-typeimpurity ions are simultaneously implanted in a boundary region betweenthe first region N+ and the second region P+. The process for implantingthe N-type impurity ions and the P-type impurity ions are performedsimultaneously with an ion implantation process for forming thesource/drain of the MOS transistor.

The first region N+ and the second region P+ form a series ofalternating ridges that are to be engaged with each other and areseparated by a predetermined interval according to the third region (N+,P+). A native oxide film 22 is formed in the third region (N+, P+) inwhich the N-type impurity ions and the P-type impurity ions aresimultaneously implanted to the polysilicon 21 by a phenomena called“butting.”

As shown in FIG. 2C, a silicide layer 23 is selectively formed on uppersurfaces of the first region N+ and the second region P+. Here, theprocess for forming the silicide layer 23 is simultaneously performedwith a process for forming silicide self-aligned to surfaces of the dataelectrode and the source/drain in order to reduce resistance values ofthe gate electrode and the source/drain of the aforementioned MOStransistor on the substrate 20.

The process for forming the self-aligned silicide in based on theprinciple that, when a refractory metal is deposited and subjected to athermal treatment process, a silicide reaction is induced on thesurfaces of the first region N+ and the second region P+ to form thesilicide layer 23, but the silicide reaction is not induced on thesurface of the third region (N+, P+) due to the presence of the nativeoxide film 22. Therefore, refractory metal on the third region remainsunreacted. By selectively removing the unreacted refractory metal on thesurface of the native oxide film 22, the silicide layer 23 can beselectively formed on the surfaces of the first region N+ and the secondregion P+. The first region N+ and the silicide layer 23 serve as oneelectrode (for example, an upper electrode) of the capacitor, and thesecond region P+ and the silicide layer 23 serve as the other electrode(for example, a lower electrode) of the capacitor.

As shown in FIG. 2D, the native oxide film 22 is selectively etched, andthe third region (N+, P+) of the polysilicon 21 is also etched, so thata contact hole 22 a for exposing the substrate 20 is formed. The processfor etching the native oxide film 22 and the third region (N+, P+) ofthe polysilicon 21 is performed by a typical photolithography process,in which a photosensitive film is formed on the native oxide film 22 andthe silicide layer 23 and exposing and developing steps using a maskform a pattern of the photosensitive film, so that the native oxide film22 exposed by the pattern of the photosensitive film and the thirdregion (N+, P+) of the polysilicon 21 may be etched. After thephotolithography process, the remaining pattern of the photosensitivefilm is stripped away. The process for etching the native oxide film 22and the third region (N+, P+) of the polysilicon 21 may also beperformed by a blanket etching process using high selection ratiosbetween the silicide layer 23 and the native oxide film 22 and betweenthe silicide layer 23 and the polysilicon 21.

As shown in FIG. 2E, an insulating layer, for example, a silicon nitridelayer 24, is deposited on an upper front surface of the substrate 20where the contact hole is formed. The process for depositing the siliconnitride layer 24 is simultaneously performed with a process fordepositing a silicon nitride layer used as an etch stop layer whenforming a contact to the aforementioned semiconductor device on thesubstrate 20. The insulating layer, i.e. the silicon nitride layer 24filling the contact hole, servers as a dielectric member of thecapacitor. Since the capacitance of the capacitor varies depending on awidth of the silicon nitride layer 24, a desired capacitance of thecapacitor can be obtained by using a simple method of suitably definingthe width of the third region (N+, P+) in which the N-type impurity ionsand the P-type impurity ions are simultaneously implanted to thepolysilicon 21.

As shown in FIG. 2F, the silicon nitride layer 24 is etched to exposethe silicide layer 23 formed on the first region N+ of the polysilicon21 and the silicide layer 23 formed on the second region P+, and then, aconductive material is formed on the upper front surface thereof andpatterned to form a ground node 25 electrically connected to thesilicide layer 23 formed on the second region P+ of the polysilicon 21and a power supply node 26 electrically connected to the first region N+of the polysilicon 21. The etching of the silicon nitride layer 24 andthe patterning of the conductive material is performed by using atypical photolithography process, i.e. by forming a photosensitive film,exposing and developing using a mask to form a pattern of thephotosensitive film, etching the conductive material exposed by thepattern of the photosensitive film, and using the silicon nitride asetch stop layer and removing the remaining pattern of the photosensitivefilm.

According to an exemplary embodiment of the present invention, since thelower electrode, the dielectric member, and the upper electrode of thecapacitor are formed during the process for forming the semiconductordevices on the substrate, the method for fabricating the capacitor canbe simplified by reducing the number of separate processes to two orfewer photolithography processes and four or fewer deposition processes,thereby increasing yield and reducing costs. In addition, since thelower electrode and the upper electrode are constructed to be separatedby a predetermined interval from each other and engaged with each otherin a series of alternating ridges, the effective surface area and, inturn, capacitance, can be maximized by increasing the number of ridgesof the lower electrode and the upper electrode, thereby enablingincreased device integration. Moreover, by using a simple method ofadjusting a width of the dielectric member between the lower electrodeand the upper electrode, a desired capacitance can be accuratelyimplemented.

It will be apparent to those skilled in the art that variousmodifications can be made in the present invention without departingfrom the spirit or scope of the invention. Thus, it is intended that thepresent invention cover such modifications provided they come within thescope of the appended claims and their equivalents.

1. A capacitor, comprising: a lower electrode, constructed of a firstpolysilicon layer patterned in a series of ridges by implanting firstconductivity type impurity ions and forming a first silicide layerstacked on an upper portion of the first polysilicon layer; an upperelectrode, constructed of a second polysilicon layer patterned in aseries of ridges by implanting second conductivity type impurity ionsand a second silicide layer stacked on an upper portion of the secondpolysilicon layer, the upper electrode being separated from the lowerelectrode by a predetermined interval and being engaged with the lowerelectrode; and a dielectric layer separating the lower and upperelectrodes.
 2. The capacitor according to claim 1, wherein thedielectric layer is a silicon nitride layer. 3-9. (canceled)
 10. Acapacitor, comprising: a lower electrode constructed of a firstpolysilicon patterned in a series of ridges; an upper electrodeconstructed of a second polysilicon patterned in a series of ridges, theupper electrode being are separated from the lower electrode by apredetermined interval and being engaged with the lower electrode; and adielectric layer separating the lower electrode and the upper electrode.11. The capacitor according to claim 10, wherein the first polysiliconand the second polysilicon are doped with impurity ions of oppositeconductivities.
 12. The capacitor according to claim 10, the lowerelectrode comprising a first silicide layer stacked on the firstpolysilicon.
 13. The capacitor according to claim 10, the upperelectrode comprising a second silicide layer stacked on the secondpolysilicon.
 14. The capacitor according to claim 10, wherein thedielectric layer is a silicon nitride layer.